(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a gate structure for a metal oxide semiconductor field effect transistor (MOSFET), device.
(2) Description of Prior Art
To continue to increase MOSFET device performance channel lengths have to be reduced to sub-0.25 micrometers (um) dimensions. Advances in specific semiconductor disciplines such as photolithography and dry etching have allowed sub-0.25 um MOSFET devices to be obtained. However to maintain high device yield as well as high device performance, specific characteristics of MOSFET elements have to be optimized. For example gate structures with widths of 0.25 um, or less, are routinely defined from polysilicon layers. The deposition conditions used for polysilicon in regards to silane or disilane flow, influence grain size as well the density of bumps or imperfections of the polysilicon layer. Polysilicon layers deposited using low silane flow rates when used for gate structures, offer higher performance than counterpart gate structures defined from polysilicon layers deposited using higher silane flows. This is due to a greater number of polysilicon bumps when compared to counterpart polysilicon layers featuring less bumps formed using higher silane flows. Polysilicon gate structures defined from low silane flow polysilicon layers offer a greater level of integrity at polysilicon gate—gate insulator interface, in addition to more uniform doping, when compared to polysilicon gate structures defined from high silane flow polysilicon layers, thus resulting in the desired enhanced device performance. However the number of bumps, or defect density of the polysilicon layer obtained via low silane flows, is higher than the level of bumps or defect density of counterpart polysilicon layer obtained via deposition using higher silane flows, therefore resulting in difficulties when attempting to define narrow width polysilicon gate structures from bumpy polysilicon layer. therefore when defining shrinking gate widths, sub-0.25 um, or gate widths of 0.22 um, the dimension and density of polysilicon bumps for the low flow vintage adversely influence the use layers deposited entirely using low silane flows, as a gate material.
This invention will describe a dual polysilicon deposition procedure allowing polysilicon gate structures for sub-0.25 um, (or 0.22 um), MOSFET devices to be formed offering higher performance then polysilicon gate structures defined from polysilicon layers deposited using only a high flow silane flow. In addition the dual polysilicon deposition procedure described in this invention will provide a gate structure with a bump density lower than counterpart polysilicon gate structures formed from polysilicon layers deposited entirely using a low silane flow. Prior art such as Gard ner et al, in U.S. Pat. No. 5,888,853, Park, in U.S. Pat. No. 6,159,820, and Samashima, in U.S. Pat. No. 6,339,010, describe methods of depositing polysilicon layers. However none of these prior art describe the novel, dual polysilicon deposition process described in this present invention, in which sub-layers of polysilicon are deposited at specific silane flows, to optimize polysilicon gate performance as well as to reduce polysilicon bump, or defect density.